`include "ascon_define.v"

module `ROUND_MERGE
     (
     input                           [`XI_W-1:0] x0_i,
     input                           [`XI_W-1:0] x1_i,
     input                           [`XI_W-1:0] x2_i,
     input                           [`XI_W-1:0] x3_i,
     input                           [`XI_W-1:0] x4_i,

     output                           [`S_W-1:0] s_o
     );

wire                                 [`XI_W-1:0] x0_w;
wire                                 [`XI_W-1:0] x1_w;
wire                                 [`XI_W-1:0] x2_w;
wire                                 [`XI_W-1:0] x3_w;
wire                                 [`XI_W-1:0] x4_w;

wire                                  [`S_W-1:0] s_w;

assign x0_w             = x0_i;
assign x1_w             = x1_i;
assign x2_w             = x2_i;
assign x3_w             = x3_i;
assign x4_w             = x4_i;

assign s_o              = s_w;

assign s_w              = {x0_w,x1_w,x2_w,x3_w,x4_w};

endmodule